`timescale 1ns/1ns
`define DATA_WIDTH 256

module ZACAU_coz(input clk,
				 input rst_n,
				 input enable,
				 input MM_end_flag,
				 output reg MM_enable,
				 output reg func,
				 output reg [21:0] r_sel,
				 output reg [7:0] M_sel_a,
				 output reg [7:0] M_sel_b,
				 output reg [7:0] A_sel_a,
				 output reg [7:0] A_sel_b,
				 output reg end_flag
				);
				
reg [49:0] state,next_state;

parameter IDLE  = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0001,
          STEP1 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0010,
		  STEP2 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0100,
		  STEP3 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_1000,
		  STEP4 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0001_0000,
		  STEP5 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0010_0000,
		  STEP6 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0100_0000,
		  STEP7 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_1000_0000,
		  STEP8 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0001_0000_0000,
		  STEP9 = 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0010_0000_0000,
		  STEP10= 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_0100_0000_0000,
		  STEP11= 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0000_1000_0000_0000,
		  STEP12= 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0001_0000_0000_0000,
		  STEP13= 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0010_0000_0000_0000,
		  STEP14= 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_0100_0000_0000_0000,
		  STEP15= 50'b00_0000_0000_0000_0000_0000_0000_0000_0000_1000_0000_0000_0000,
		  STEP16= 50'b00_0000_0000_0000_0000_0000_0000_0000_0001_0000_0000_0000_0000,
		  STEP17= 50'b00_0000_0000_0000_0000_0000_0000_0000_0010_0000_0000_0000_0000,
		  STEP18= 50'b00_0000_0000_0000_0000_0000_0000_0000_0100_0000_0000_0000_0000,
		  STEP19= 50'b00_0000_0000_0000_0000_0000_0000_0000_1000_0000_0000_0000_0000,
		  STEP20= 50'b00_0000_0000_0000_0000_0000_0000_0001_0000_0000_0000_0000_0000,
		  STEP21= 50'b00_0000_0000_0000_0000_0000_0000_0010_0000_0000_0000_0000_0000,
		  STEP22= 50'b00_0000_0000_0000_0000_0000_0000_0100_0000_0000_0000_0000_0000,
		  STEP23= 50'b00_0000_0000_0000_0000_0000_0000_1000_0000_0000_0000_0000_0000,
		  STEP24= 50'b00_0000_0000_0000_0000_0000_0001_0000_0000_0000_0000_0000_0000,
		  STEP25= 50'b00_0000_0000_0000_0000_0000_0010_0000_0000_0000_0000_0000_0000,
		  STEP26= 50'b00_0000_0000_0000_0000_0000_0100_0000_0000_0000_0000_0000_0000,
		  STEP27= 50'b00_0000_0000_0000_0000_0000_1000_0000_0000_0000_0000_0000_0000,
		  STEP28= 50'b00_0000_0000_0000_0000_0001_0000_0000_0000_0000_0000_0000_0000,
		  STEP29= 50'b00_0000_0000_0000_0000_0010_0000_0000_0000_0000_0000_0000_0000,
		  STEP30= 50'b00_0000_0000_0000_0000_0100_0000_0000_0000_0000_0000_0000_0000,
		  STEP31= 50'b00_0000_0000_0000_0000_1000_0000_0000_0000_0000_0000_0000_0000,
		  STEP32= 50'b00_0000_0000_0000_0001_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP33= 50'b00_0000_0000_0000_0010_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP34= 50'b00_0000_0000_0000_0100_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP35= 50'b00_0000_0000_0000_1000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP36= 50'b00_0000_0000_0001_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP37= 50'b00_0000_0000_0010_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP38= 50'b00_0000_0000_0100_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP39= 50'b00_0000_0000_1000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP40= 50'b00_0000_0001_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP41= 50'b00_0000_0010_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP42= 50'b00_0000_0100_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP43= 50'b00_0000_1000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP44= 50'b00_0001_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP45= 50'b00_0010_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP46= 50'b00_0100_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP47= 50'b00_1000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP48= 50'b01_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
		  STEP49= 50'b10_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
		  
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		state <= IDLE;
	end
	else
	begin
		state <= next_state;
	end
end

always @(*)
begin
	case(state)
	IDLE   :
			begin
				if((enable) & (!end_flag))
					next_state = STEP1;
				else
					next_state = IDLE;
			end
	STEP1  :
			begin
				if(MM_end_flag)
					next_state = STEP2;
				else
					next_state = STEP1;
			end
	STEP2  :
			begin
				if(MM_end_flag)
					next_state = STEP3;
				else
					next_state = STEP2;
			end
	STEP3  :
			begin
				next_state = STEP4;
			end
	STEP4  :
			begin
				if(MM_end_flag)
					next_state = STEP5;
				else
					next_state = STEP4;
			end	
	STEP5  :
		 	begin
				next_state = STEP6;
			end	
	STEP6  :
		 	begin
				next_state = STEP7;
			end	
	STEP7  :
			begin
				if(MM_end_flag)
					next_state = STEP8;
				else
					next_state = STEP7;
			end		
	STEP8  :
			begin
				next_state = STEP9;
			end	
	STEP9  :
			begin
				next_state = STEP10;
			end	
	STEP10 :
			begin
				next_state = STEP11;
			end	
	STEP11 :
			begin
				if(MM_end_flag)
					next_state = STEP12;
				else
					next_state = STEP11;
			end
	STEP12 :
			begin
				next_state = STEP13;
			end
	STEP13 :
			begin
				next_state = STEP14;
			end	
	STEP14 :
			begin
				next_state = STEP15;
			end	
	STEP15 :
			begin
				if(MM_end_flag)
					next_state = STEP16;
				else
					next_state = STEP15;
			end
	STEP16 :
			begin
				next_state = STEP17;
			end
	STEP17 :
			begin
				next_state = STEP18;
			end
	STEP18 :
			begin
				next_state = STEP19;
			end
	STEP19 :
			begin
				if(MM_end_flag)
					next_state = STEP20;
				else
					next_state = STEP19;
			end
	STEP20 :
			begin
				next_state = STEP21;
			end
	STEP21 :
			begin
				next_state = STEP22;
			end
	STEP22 :
			begin
				if(MM_end_flag)
					next_state = STEP23;
				else
					next_state = STEP22;
			end
	STEP23 :
			begin
				if(MM_end_flag)
					next_state = STEP24;
				else
					next_state = STEP23;
			end
	STEP24 :
			begin
				if(MM_end_flag)
					next_state = STEP25;
				else
					next_state = STEP24;
			end
	STEP25 :
			begin
				next_state = STEP26;
			end
	STEP26 :
			begin
				next_state = STEP27;
			end
	STEP27 :
			begin
				if(MM_end_flag)
					next_state = STEP28;
				else
					next_state = STEP27;
			end
	STEP28 :
			begin
				if(MM_end_flag)
					next_state = STEP29;
				else
					next_state = STEP28;
			end
	STEP29 :
			begin
				next_state = STEP30;
			end
	STEP30 :
			begin
				next_state = STEP31;
			end
	STEP31 :
			begin
				next_state = STEP32;
			end
	STEP32 :
			begin
				next_state = STEP33;
			end
	STEP33 :
			begin
				next_state = STEP34;
			end
	STEP34 :
			begin
				if(MM_end_flag)
					next_state = STEP35;
				else
					next_state = STEP34;
			end
	STEP35 :
			begin
				next_state = STEP36;
			end
	STEP36 :
			begin
				next_state = STEP37;
			end
	STEP37 :
			begin
				if(MM_end_flag)
					next_state = STEP38;
				else
					next_state = STEP37;
			end
	STEP38 :
			begin
				next_state = STEP39;
			end
	STEP39 :
			begin
				next_state = STEP40;
			end
	STEP40 :
			begin
				next_state = STEP41;
			end
	STEP41 :
			begin
				next_state = STEP42;
			end
	STEP42 :
			begin
				next_state = STEP43;
			end
	STEP43 :
			begin
				next_state = STEP44;
			end
	STEP44 :
			begin
				next_state = STEP45;
			end
	STEP45 :
			begin
				next_state = STEP46;
			end
	STEP46 :
			begin
				next_state = STEP47;
			end
	STEP47 :
			begin
				next_state = STEP48;
			end
	STEP48 :
			begin
				next_state = STEP49;
			end
	STEP49 :
			begin
				next_state = IDLE;
			end
	default:
			begin
				next_state = IDLE;
			end
	endcase
end


always @(*)
begin
		case(state)
		/*IDLE:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		*/
		/*REG:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end*/
		STEP1:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;//t3
				M_sel_b = 8'b0_0_0_1_0_0_0_0;//t4
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP2:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;//t3
				M_sel_b = 8'b0_0_0_0_0_0_1_0;//t1
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP3:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;//t2
				A_sel_b = 8'b0_0_1_0_0_0_0_0;//t5
			end
		STEP4:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_1_0;//t1
				M_sel_b = 8'b0_0_0_0_0_0_1_0;//t1
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP5:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_1_0_0_0_0;//t4
				A_sel_b = 8'b0_0_0_0_1_0_0_0;//t3
			end
		STEP6:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;//t2
				A_sel_b = 8'b0_0_1_0_0_0_0_0;//t5
			end
		STEP7:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_1_0;//t1
				M_sel_b = 8'b0_0_0_0_0_0_1_0;//t1
				A_sel_a = 8'b0_0_0_1_0_0_0_0;//t4
				A_sel_b = 8'b0_1_0_0_0_0_0_0;//t6
			end
		STEP8:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;//t1
				A_sel_b = 8'b0_0_0_0_1_0_0_0;//t3
			end
		STEP9:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;//t1
				A_sel_b = 8'b0_1_0_0_0_0_0_0;//t6
			end
		STEP10:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_1_0_0_0_0_0_0;//t6
				A_sel_b = 8'b0_0_0_0_1_0_0_0;//t3
			end
		STEP11:
			begin
				M_sel_a = 8'b0_1_0_0_0_0_0_0;//t6
				M_sel_b = 8'b0_0_0_0_0_1_0_0;//t2
				A_sel_a = 8'b0_0_0_0_1_0_0_0;//t3
				A_sel_b = 8'b0_0_0_1_0_0_0_0;//t4
			end
		STEP12:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;//t2
				A_sel_b = 8'b0_0_1_0_0_0_0_0;//t5
			end
		STEP13:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_1_0_0_0_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		STEP14:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		STEP15:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;
				M_sel_b = 8'b0_0_1_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP16:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_1_0_0_0_0_0;
				A_sel_b = 8'b0_1_0_0_0_0_0_0;
			end
		STEP17:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP18:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_1_0;
			end
		STEP19:
			begin
				M_sel_a = 8'b0_0_0_0_0_1_0_0;
				M_sel_b = 8'b0_0_0_0_1_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP20:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_1_0_0_0_0_0_0;
			end
		STEP21:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP22:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;
				M_sel_b = 8'b0_0_0_0_1_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP23:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;
				M_sel_b = 8'b0_0_0_1_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP24:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_1_0;
				M_sel_b = 8'b0_0_0_0_1_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP25:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		STEP26:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_1_0_0_0_0;
				A_sel_b = 8'b0_1_0_0_0_0_0_0;
			end
		STEP27:
			begin
				M_sel_a = 8'b0_0_0_0_0_1_0_0;
				M_sel_b = 8'b0_1_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP28:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;
				M_sel_b = 8'b0_0_0_0_1_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		STEP29:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_1_0_0_0_0_0_0;
			end
		STEP30:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP31:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP32:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP33:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_1_0_0_0_0_0_0;
			end
		STEP34:
			begin
				M_sel_a = 8'b0_0_0_0_1_0_0_0;
				M_sel_b = 8'b0_0_0_0_1_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;
				A_sel_b = 8'b0_0_0_0_0_0_1_0;
			end
		STEP35:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_1_0;
				A_sel_b = 8'b0_0_0_0_0_0_1_0;
			end
		STEP36:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_1_0_0;
			end
		STEP37:
			begin
				M_sel_a = 8'b0_1_0_0_0_0_0_0;
				M_sel_b = 8'b0_1_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_1_0_0_0_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		STEP38:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_0_0_0_1_0_0_0;
			end
		STEP39:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		STEP40:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_0_0_0_0_1_0_0;
			end
		STEP41:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_1_0_0;
				A_sel_b = 8'b0_0_0_0_0_1_0_0;
			end
		STEP42:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_0_1_0_0_0;
			end
		STEP43:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_0_1_0_0_0;
			end
		STEP44:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_0_1_0_0_0;
			end
		STEP45:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_1_0_0_0;
				A_sel_b = 8'b0_0_0_0_1_0_0_0;
			end
		STEP46:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_1_0_0_0_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP47:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_1_0_0_0_0;
				A_sel_b = 8'b0_0_0_1_0_0_0_0;
			end
		STEP48:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_1_0_0_0_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		STEP49:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_1_0_0_0_0_0;
				A_sel_b = 8'b0_0_1_0_0_0_0_0;
			end
		default:
			begin
				M_sel_a = 8'b0_0_0_0_0_0_0_0;
				M_sel_b = 8'b0_0_0_0_0_0_0_0;
				A_sel_a = 8'b0_0_0_0_0_0_0_0;
				A_sel_b = 8'b0_0_0_0_0_0_0_0;
			end
		endcase
end

always @(*)
begin
		case(state)
		/*
		IDLE  : 
			 	r_sel = 22'b0;
		*/
		/*REG	  :
				r_sel = 22'b000_00_011_011_11_11_11_00;*/
		STEP1 :
				r_sel = 22'b000_10_000_000_000_000_000_00;
		STEP2 :
				r_sel = 22'b000_00_000_000_010_000_000_00;
		STEP3 :
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP4 :
				r_sel = 22'b000_00_000_010_000_000_000_00;
		STEP5 :
			 	r_sel = 22'b000_00_000_001_000_000_000_00;
		STEP6 :
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP7 :
				if(MM_end_flag)
				r_sel = 22'b000_00_000_001_000_000_010_00;
				else
				r_sel = 22'b000_00_000_000_000_000_010_00;
		STEP8 :
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP9 :
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP10:
				r_sel = 22'b000_01_000_000_000_000_000_00;
		STEP11:
				if(MM_end_flag)
				r_sel = 22'b000_10_000_000_001_000_000_00;
				else
				r_sel = 22'b000_10_000_000_000_000_000_00;
		STEP12:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP13:
				r_sel = 22'b000_00_001_000_000_000_000_00;
		STEP14:
				r_sel = 22'b000_00_001_000_000_000_000_00;
		STEP15:
			 	r_sel = 22'b000_00_010_000_000_000_000_00;
		STEP16:
				r_sel = 22'b000_00_001_000_000_000_000_00;
		STEP17:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP18:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP19:
				r_sel = 22'b000_00_000_000_000_010_000_00;
		STEP20:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP21:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP22:
				r_sel = 22'b000_00_000_000_010_000_000_00;
		STEP23:
				r_sel = 22'b000_10_000_000_000_000_000_00;
		STEP24:
				r_sel = 22'b000_00_000_010_000_000_000_00;
		STEP25:
			 	r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP26:
				r_sel = 22'b000_01_000_000_000_000_000_00;
		STEP27:
				r_sel = 22'b000_00_010_000_000_000_000_00;
		STEP28:
				r_sel = 22'b000_00_000_000_000_010_000_00;
		STEP29:
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP30:
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP31:
				r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP32:
				r_sel = 22'b000_01_000_000_000_000_000_00;
		STEP33:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP34:
				if(MM_end_flag)
				r_sel = 22'b000_00_000_000_010_000_001_00;
				else
				r_sel = 22'b000_00_000_000_010_000_000_00;
		STEP35:
			 	r_sel = 22'b000_00_000_000_000_000_001_00;
		STEP36:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP37:
				if(MM_end_flag)
				r_sel = 22'b000_00_001_000_010_000_000_00;
				else
				r_sel = 22'b000_00_000_000_010_000_000_00;
		STEP38:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP39:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP40:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP41:
				r_sel = 22'b000_00_000_000_000_001_000_00;
		STEP42:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP43:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP44:
				r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP45:
			 	r_sel = 22'b000_00_000_000_001_000_000_00;
		STEP46:
				r_sel = 22'b000_00_000_001_000_000_000_00;
		STEP47:
				r_sel = 22'b000_00_000_001_000_000_000_00;
		STEP48:
				r_sel = 22'b000_00_001_000_000_000_000_00;
		STEP49:
				r_sel = 22'b000_00_001_000_000_000_000_00;
		default:
				r_sel = 22'b0;
		endcase
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		MM_enable <= 1'b0;
	end
	else
	begin
		case(next_state)
		IDLE  :
					MM_enable <= 1'b0;
		/*REG	  :
					MM_enable <= 1'b0;*/
		STEP1 :
		/*
				if(state == REG)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		*/
				if(state == IDLE)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP2 :
				if(state == STEP1)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP3 :
					MM_enable <= 1'b0;
		STEP4 :
				if(state == STEP3)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP5 :
					MM_enable <= 1'b0;
		STEP6 :
					MM_enable <= 1'b0;
		STEP7 :
				if(state == STEP6)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP8 :
					MM_enable <= 1'b0;
		STEP9 :
					MM_enable <= 1'b0;
		STEP10:
					MM_enable <= 1'b0;
		STEP11:
				if(state == STEP10)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP12:
					MM_enable <= 1'b0;
		STEP13:
					MM_enable <= 1'b0;
		STEP14:
					MM_enable <= 1'b0;
		STEP15:
				if(state == STEP14)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP16:
					MM_enable <= 1'b0;
		STEP17:
					MM_enable <= 1'b0;
		STEP18:
					MM_enable <= 1'b0;
		STEP19:
				if(state == STEP18)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP20:
					MM_enable <= 1'b0;
		STEP21:
					MM_enable <= 1'b0;
		STEP22:
				if(state == STEP21)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP23:
				if(state == STEP22)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP24:
				if(state == STEP23)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP25:
					MM_enable <= 1'b0;
		STEP26:
					MM_enable <= 1'b0;
		STEP27:
				if(state == STEP26)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP28:
				if(state == STEP27)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP29:
					MM_enable <= 1'b0;
		STEP30:
					MM_enable <= 1'b0;
		STEP31:
					MM_enable <= 1'b0;
		STEP32:
					MM_enable <= 1'b0;
		STEP33:
					MM_enable <= 1'b0;
		STEP34:
				if(state == STEP33)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;
		STEP35:
					MM_enable <= 1'b0;
		STEP36:
					MM_enable <= 1'b0;
		STEP37:
				if(state == STEP36)
					MM_enable <= 1'b1;
				else
					MM_enable <= 1'b0;	
		STEP38:
					MM_enable <= 1'b0;
		STEP39:
					MM_enable <= 1'b0;
		STEP40:
					MM_enable <= 1'b0;
		STEP41:
					MM_enable <= 1'b0;
		STEP42:
					MM_enable <= 1'b0;
		STEP43:
					MM_enable <= 1'b0;
		STEP44:
					MM_enable <= 1'b0;
		STEP45:
					MM_enable <= 1'b0;
		STEP46:
					MM_enable <= 1'b0;
		STEP47:
					MM_enable <= 1'b0;
		STEP48:
					MM_enable <= 1'b0;
		STEP49:
					MM_enable <= 1'b0;
		default:
					MM_enable <= 1'b0;
		endcase
	end
end

always @(*)
begin
		case(state)
		/*
		IDLE  :
					func = 1'b0;
		*/
		/*REG	  :
					func = 1'b0;*/
		/*
		STEP1 :
					func = 1'b0;
		STEP2 :
					func = 1'b0;
		STEP3 :
					func = 1'b0;
		STEP4 :
					func = 1'b0;
		*/
		STEP5 :
					func = 1'b1;	
		STEP6 :	
					func = 1'b1;
		STEP7 :
					func = 1'b1;
		STEP8 :
					func = 1'b1;
		STEP9 :
					func = 1'b1;
		STEP10:
					func = 1'b1;					
		STEP11:
					func = 1'b1;
		STEP12:
					func = 1'b1;
		/*	
		STEP13:
					func = 1'b0;	
		STEP14:
					func = 1'b0;
		STEP15:
					func = 1'b0;
		STEP16:
					func = 1'b0;
		STEP17:
					func = 1'b0;
		*/
		STEP18:
					func = 1'b1;
		/*
		STEP19:
					func = 1'b0;		
		STEP20:
					func = 1'b0;
		*/					
		STEP21:
					func = 1'b1;
		/*
		STEP22:
					func = 1'b0;	
		STEP23:
					func = 1'b0;	
		STEP24:
					func = 1'b0;
		*/
		STEP25:
					func = 1'b1;
		STEP26:
					func = 1'b1;
		/*
		STEP27:
					func = 1'b0;
		STEP28:
					func = 1'b0;
		STEP29:
					func = 1'b0;
		*/	
		STEP30:
					func = 1'b1;					
		STEP31:
					func = 1'b1;
		STEP32:
					func = 1'b1;	
		STEP33:
					func = 1'b1;	
		/*
		STEP34:
					func = 1'b0;
		STEP35:
					func = 1'b0;
		*/
		STEP36:
					func = 1'b1;
		/*
		STEP37:
					func = 1'b0;
		*/
		STEP38:
					func = 1'b1;
		STEP39:
					func = 1'b1;	
		/*
		STEP40:
					func = 1'b0;					
		STEP41:
					func = 1'b0;
		STEP42:
					func = 1'b0;	
		STEP43:
					func = 1'b0;	
		STEP44:
					func = 1'b0;
		STEP45:
					func = 1'b0;
		STEP46:
					func = 1'b0;
		STEP47:
					func = 1'b0;
		STEP48:
					func = 1'b0;
		STEP49:
					func = 1'b0;	
		*/						
		default:
					func = 1'b0;
		endcase
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		end_flag <= 1'b0;
	end
	else if(state == STEP49)
	begin
		end_flag <= 1'b1;
	end
	else
	begin
		end_flag <= 1'b0;
	end
end

endmodule
